Fabricating smaller, more densely packed devices having greater computing capability is a continuing objective in building semiconductor devices. For example, scaling of devices has been instrumental in improvements in speed, power consumption and utilization of expensive area on a chip. However, as newer technology nodes are being designed, scaling of features is becoming more problematic.
To improve area scaling as pitch scaling slows, track count of the standard cell libraries can be reduced. However, track reduction beyond 6 T (6 tracks) is difficult due to lithographic overlay tolerances which can short wiring lines. For example, cut metal lines need to be separated to ensure that devices do not short together; however, conventional photolithographic processes cannot keep up with the current scaling, effectively consuming valuable area on the chip and allowing overlay issues that result in shorting.